Implementation of a tunable heterodyne notch filter

Author

Azam, Asad ; Sasidaran, Dhinesh ; Nelson, Karl E. ; Ford, Gary E. ; Choi, Seong-Jhin ; Johnson, Louis ; Soderstrand, Michacl A.

Author_Institution

Sch. of Electr. & Comput. Eng., Oklahoma State Univ., Stillwater, OK, USA

Volume

1

fYear

1999

fDate

24-27 Oct. 1999

Firstpage

169

Abstract

Simple hardware implementations of three key elements, (1) a fixed-coefficient prototype filter. (2) the digital up-converter, and (3) a digital down-converter are proposed for realization in FPGAs or ASICs. Through layout and simulation the feasibility of a tunable heterodyne notch filter is established in which three up-converters, four notch filters and three down-converters are combined to build a complete tunable heterodyne notch filter with more flexibility and less complexity than conventional tunable notch filters.

Keywords

IIR filters; circuit complexity; circuit tuning; field programmable gate arrays; high-pass filters; notch filters; ASIC; FPGA; complexity; digital down-converter; digital up-converter; fixed-coefficient prototype filter; flexibility; hardware implementations; layout; simulation; tunable heterodyne notch filter; Art; Computational modeling; Digital filters; Field programmable gate arrays; Finite impulse response filter; Hardware; IIR filters; Prototypes; Transfer functions; Tunable circuits and devices;

fLanguage

English

Publisher

ieee

Conference_Titel

Signals, Systems, and Computers, 1999. Conference Record of the Thirty-Third Asilomar Conference on

Conference_Location

Pacific Grove, CA, USA

ISSN

1058-6393

Print_ISBN

0-7803-5700-0

Type

conf

DOI

10.1109/ACSSC.1999.832316

Filename

832316