DocumentCode
1835797
Title
Hybrid hierarchical timing closure methodology for a high performance and low power DSP
Author
Shi, Kaijian ; Godwin, Graig
Author_Institution
Professional Services, Synopsis Inc., Dallas, TX, USA
fYear
2003
fDate
2-6 June 2003
Firstpage
850
Lastpage
855
Abstract
A hybrid hierarchical timing closure methodology has been developed to combine strength of the subchip based hierarchical timing closure method and flat design based logic-physical combined optimization method for a 1.5 million gates, high performance and ultra-low power DSP which has been used in a number of wireless applications. The principle and the implementation details of the methodology are provided.
Keywords
circuit optimisation; digital signal processing chips; integrated circuit design; integrated circuit layout; logic partitioning; timing; DSP; chip integration; digital signal processing; flat design based logic-physical combined optimization method; hybrid hierarchical timing closure methodology; placement optimization; subchip based timing closure; wireless application; Assembly; Design methodology; Design optimization; Digital signal processing; Digital signal processing chips; Optimization methods; Permission; Repeaters; Routing; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2003. Proceedings
Print_ISBN
1-58113-688-9
Type
conf
DOI
10.1109/DAC.2003.1219138
Filename
1219138
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