Title :
A new retiming algorithm for cycle-time minimization in synchronous logic synthesis
Author :
Zhang, Yan ; Yu, Mingyan ; Ye, Yizheng
Author_Institution :
Microelectron. Center, Harbin Inst. of Technol., China
Abstract :
A new retiming algorithm for cycle-time minimization is given in this paper. In this algorithm, it is proved that the existence of a feasible retiming transformation can be computed in O(|E|* (num-ele + num-ver)) time for general synchronous Boolean networks
Keywords :
logic design; minimisation of switching nets; timing; Boolean network; cycle-time minimization; retiming algorithm; synchronous logic synthesis; Circuits; Clocks; Computer networks; Logic; Microelectronics; Minimization methods; Physics computing; Registers; Signal generators;
Conference_Titel :
Solid-State and Integrated Circuit Technology, 1995 4th International Conference on
Conference_Location :
Beijing
Print_ISBN :
0-7803-3062-5
DOI :
10.1109/ICSICT.1995.503374
