Title :
Reducing the logic-level of combinational circuits
Author :
Zeng, Xianjun ; Yu, Mingyan ; Zhang, Yan ; Ye, Yizheng
Author_Institution :
Microelectron. Center, Harbin Inst. of Technol., China
Abstract :
The Boolean function factoring method with the objective of logic-level minimization is discussed in this paper. An optimization algorithm for combinational logic circuits is proposed based on Lawler´s clustering algorithm and sublogic structural transformation
Keywords :
Boolean functions; circuit optimisation; combinational circuits; logic design; minimisation of switching nets; Boolean function factoring; clustering algorithm; combinational circuit; logic-level minimization; optimization; sublogic structural transformation; Boolean functions; Clustering algorithms; Combinational circuits; Cost function; Delay; Logic circuits; Logic functions; Microelectronics; Minimization methods; Optimization methods;
Conference_Titel :
Solid-State and Integrated Circuit Technology, 1995 4th International Conference on
Conference_Location :
Beijing
Print_ISBN :
0-7803-3062-5
DOI :
10.1109/ICSICT.1995.503378
