Segmentation strategies for low power implementation of digital filters

This paper describes a generic algorithm for low power implementation of digital filers. The algorithm reduces power through a reduction in the amount of switched capacitance within the multiplier section of the filter. This reduction in turn is achieved through the segmentation of a given coefficient into two primitive sub-components. The algorithm is suitable for prototyping as an intellectual property core with high degree of parameterisability. Hence making the core extremely valuable for rapid system-on-chip implementation for multimedia/wireless applications. The paper describes the algorithm, its adaptability to different representation formats, and provides results which show significant power saving with different wordlengths and filter orders. The paper also indicates overheads due to the additional shift operations. Results indicate power savings in the range of 27-85% even after including the effects of these overheads.