DocumentCode
1836301
Title
A hardware accelerated system for deep packet inspection
Author
Rao, Adarsha ; Udupa, Pramod
Author_Institution
Indian Inst. of Sci., Bangalore, India
fYear
2010
fDate
26-28 July 2010
Firstpage
89
Lastpage
92
Abstract
We implemented a hardware accelerated system for deep packet inspection. The proposed system makes use of operation level and connection level parallelism to achieve a maximum processing rate of 595.2Mb/s. The system supports 25 mandatory patterns running at 125 MHz on a Xilinx Virtex 5 FPGA.
Keywords
field programmable gate arrays; parallel architectures; security of data; Xilinx Virtex 5 FPGA; connection level parallelism; deep packet inspection; hardware accelerated system; Computer architecture; Context; Field programmable gate arrays; Hardware; Hardware design languages; Inspection; Software;
fLanguage
English
Publisher
ieee
Conference_Titel
Formal Methods and Models for Codesign (MEMOCODE), 2010 8th IEEE/ACM International Conference on
Conference_Location
Grenoble
Print_ISBN
978-1-4244-7885-9
Electronic_ISBN
978-1-4244-7886-6
Type
conf
DOI
10.1109/MEMCOD.2010.5558646
Filename
5558646
Link To Document