A high throughput parallel architecture for category specific Deep Packet Inspection

This paper describes a Field Programmable Gate Array hardware based Deep Packet Inspection Engine that uses regular expression matchers to simultaneously categorize and look for malicious signatures in Ethernet packets. This was a submission to the 2010 MEMOCODE Design Contest. It is the fastest Xilinx FPGA based design with a throughput of 734 Mbit/sec and the 2^nd fastest overall, out of all designs submitted from teams worldwide. A unique feature of this architecture is that the high throughput is independent of both the number of categorizers and the density of malicious signatures.