Title :
Exploring the impact of logic synthesis on area, delay and power dissipation of CMOS circuits
Author :
Macii, Alberto ; Macii, Enrico
Author_Institution :
Dipt. di Autom. e Inf., Politecnico di Torino, Italy
Abstract :
Area, delay and power dissipation are currently the major design constraints to be met during the design of digital VLSI systems. In this paper we address the problem of studying the impact of different types of logic optimization techniques, as well as technology mapping options, on the aforementioned parameters of the design space. More specifically, we provide an experimental analysis of the area-delay-power trade-off for a number of benchmark circuits that will provide a useful source of information for designers who are commonly adopting automatic synthesis tools for the development of their applications.
Keywords :
CMOS logic circuits; VLSI; circuit optimisation; integrated circuit design; logic CAD; CMOS circuits; area-delay-power trade-off; automatic synthesis tools; benchmark circuits; design constraints; digital VLSI systems; logic optimization techniques; logic synthesis; power dissipation; technology mapping options; CMOS logic circuits; Circuit synthesis; Delay; Design optimization; Information resources; Isolation technology; Libraries; Logic design; Power dissipation; Space technology;
Conference_Titel :
Signals, Systems, and Computers, 1999. Conference Record of the Thirty-Third Asilomar Conference on
Conference_Location :
Pacific Grove, CA, USA
Print_ISBN :
0-7803-5700-0
DOI :
10.1109/ACSSC.1999.832357
