DocumentCode
1836466
Title
A cost-effective assembly process for flip chips on FR-4
Author
Feustel, F. ; Lauterwald, B. ; Grätz, P. ; Meusel, E.
Author_Institution
Semicond. & Microsyst. Technol. Lab., Tech. Univ. Dresden, Germany
fYear
1998
fDate
25-28 May 1998
Firstpage
427
Lastpage
433
Abstract
The application of flip chips is an attractive approach for many innovative products-especially portable systems. For cost reasons, the flip chip assembly has to be integrated into the existing surface mount technology. In this work, the main aspects of an SMT compatible assembly process for flip chips on FR-4 were studied. Test chips up to 9.6 mm edge length were mounted. Two types of substrates were used successfully: FR-4 with SIPAD solder deposits and FR-4 with modified solder mask patterns. The bumping process of the chips as well as the layout of the chips and the substrates is introduced. The placement and the reflow soldering were performed with regular equipment. Important issues of the soldering and the flux selection are discussed. Complete underfilling of the attached flip chips is necessary to achieve a sufficient reliability level. A test methodology is presented to visualize and assess the flow behavior of underfill materials. Measurement results of three representative underfills are discussed. Finally, first reliability results are introduced
Keywords
circuit reliability; flip-chip devices; microassembling; printed circuit manufacture; reflow soldering; surface mount technology; 9.6 mm; FR-4 substrate; SIPAD solder deposits; SMT compatible assembly process; bumping process; cost-effective assembly process; flip chip assembly; flow behavior; flux selection; modified solder mask patterns; placement; reflow soldering; reliability; surface mount technology; test methodology; underfilling; Assembly systems; Copper; Costs; Flip chip; Laboratories; Reflow soldering; Sputtering; Substrates; Surface-mount technology; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronic Components & Technology Conference, 1998. 48th IEEE
Conference_Location
Seattle, WA
ISSN
0569-5503
Print_ISBN
0-7803-4526-6
Type
conf
DOI
10.1109/ECTC.1998.678729
Filename
678729
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