Design of highly linear multipliers using floating gate transistors and/or source degeneration resistor

Compact schemes to implement two highly linear four quadrant CMOS transconductance multipliers are presented in this work. They are based on floating gate transistors and/or source degeneration resistor which provide high linearity and wide input, output swing. Two cross connected differential pairs are used as current steering elements which provide continuous adjustable gain. Unlike the conventional multipliers the proposed techniques generate currents that have mostly linear terms and reduce cancellation of non-linear terms at the output. Hence they are very linear and non-vulnerable to practical problems like mismatch and finite output impedance. Simulation and Experimental results are provided which validate the proposed schemes.