A phase-frequency detector and a charge pump design for PLL applications

An improved phase frequency detector (PFD) and a novel charge pump (CP) for phase locked loop (PLL) applications are presented. Implemented in a CMOS 0.13 mum technology, the PFD and the CP dissipate 3.73 mW and a 460 muW DC power from a IV supply, respectively. The occupied chip area of the PFD is 68times24 mum², and that of the CP is 68times23 mum². With a spurious free dynamic range of a 80 dBc, a phase noise of a -95 dBc/Hz at 100 kHz offset, a low power and a small layout area the presented PFD and CP are suitable for integrated radio applications operating between 2.4 GHz and 10 GHz, such as 802.11 and WiMax for example.