Analysis and performance evaluation of area-efficient true random bit generators on FPGAs

In this paper, fully digital true random bit generators (TRBGs) targeting area-efficient FPGA implementations are analyzed and evaluated. In this analysis, a very general class of TRBGs is considered that is based on the well-known sampling oscillators used as a building block. A qualitative model is discussed and applied to derive simple design guidelines to implement low-area TRBGs. Extensive measurements are made on TRBGs implemented on Altera Cyclone FPGAs. Results confirm that properly designed TRBGs based on FPGAs can achieve very high-quality random sequences with low area occupation.