Title :
An improved processing core for MIPA-processor family
Author :
Paasio, A. ; Laiho, M.
Author_Institution :
Dept. of Inf. Technol., Univ. of Turku, Turku, Finland
Abstract :
This paper describes a new and economical circuit realization for binary processing core that can be used to improve the reliability and power consumption of very large massively parallel processor arrays. The circuit arrangement does not need dynamic nodes for operation and is therefore more suitable for reliable asynchronous computing.
Keywords :
asynchronous circuits; parallel processing; MIPA processor family; asynchronous computing; binary processing core; circuit arrangement; massively parallel processor arrays; Array signal processing; Cellular networks; Circuit testing; Energy consumption; Information technology; Integrated circuit reliability; Logic circuits; Power generation economics; Signal processing; Switches; 3D integration; binary processing; processor arrays;
Conference_Titel :
Cellular Nanoscale Networks and Their Applications (CNNA), 2010 12th International Workshop on
Conference_Location :
Berkeley, CA
Print_ISBN :
978-1-4244-6679-5
DOI :
10.1109/CNNA.2010.5430271
