A fast locking digital phase-locked loop using programmable charge pump

Author

Ali, M. ; Elsemary, H. ; Shawkey, H. ; Zekry, A.

Author_Institution

Microelectron. Dept., Electron. Res. Inst. (ERI), Cairo, Egypt

fYear

2010

fDate

Nov. 30 2010-Dec. 2 2010

Firstpage

135

Lastpage

138

Abstract

A proposed fast locking digital phase-locked loop (DPLL) is designed and simulated in this paper. The proposed topology based on converting the difference between the input frequency and the output frequency into a 3-bit code. This code is used to control a programmable charge pump (PCP) output current. As the difference between the two frequencies decreases, the PCP output current decreases to obtain smooth PLL locking. As locking is achieved, the PCP operates with its conventional current. The proposed DPLL is designed using UMC 130nm CMOS process with a 1.2V power supply. It operates in the frequency range 250MHz-1.75GHz. Over this frequency range a locking time reduction in the range of 35.7%-66.6% was achieved compared with conventional DPLL.

Keywords

CMOS digital integrated circuits; digital phase locked loops; CMOS process; fast locking digital phase locked loop; frequency 250 MHz to 1.75 GHz; programmable charge pump; size 130 nm; smooth PLL locking; voltage 1.2 V; Charge pumps; Frequency control; Phase frequency detector; Phase locked loops; Radiation detectors; Time frequency analysis; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Engineering and Systems (ICCES), 2010 International Conference on

Conference_Location

Cairo

Print_ISBN

978-1-4244-7040-2

Type

conf

DOI

10.1109/ICCES.2010.5674840

Filename

5674840