Predictive coding on-sensor compression

This paper presents the design and measurements of a predictive coding on-sensor compression CMOS imager. Predictive coding is employed to decorrelate the image. The prediction operations are performed in the analog domain to avoid quantization noise and to decrease the area complexity of the circuit. The decorrelated image is encoded with a bank of column-parallel entropy encoders. Each encoder is combined with a single-slope analog-to-digital converter (ADC) to reduce area complexity and power consumption. The area savings resulting from such combination allow to integrate an ADC and an entropy encoder at the column level. A prototype chip was fabricated in a 0.35 mum CMOS process. The output of the chip is a compressed bit stream. The test chip occupies a silicon area of 2.60 mm times 5.96 mm which includes an 80 times 44 APS array. Tests of the fabricated chip demonstrate the validity of the design.