An analog self-similitude edge-filtering processor for multiple-resolution image perception

A pixel-parallel self-similitude edge-filtering architecture has been developed for multiple-resolution image perception employing the directional-edge-based representation. The self-similitude organization has enabled pixel-by-pixel multiple-resolution image filtering with minimal complexity in interconnects. As a result, it has become possible to accomplish (l/2)ⁿ-resolution directional edge filtering in (n+2) steps. An analog proof-of-concept chip implemented using floating-gate MOS technology capable of performing four directional edge filtering at full, half and quarter resolutions was designed and fabricated in a 0.35mum 3-metal CMOS technology. The concept has been experimentally verified using the fabricated chip and the four directional edge filtering at multiple resolutions at a rate of 300 frames/sec was demonstrated by measurement.