• DocumentCode
    1837854
  • Title

    Compression flow modeling of underfill encapsulants for low cost flip chip assembly

  • Author

    Pascarella, Nathan W. ; Baldwin, Daniel F.

  • Author_Institution
    George W. Woodruff Sch. of Mech. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
  • fYear
    1998
  • fDate
    25-28 May 1998
  • Firstpage
    463
  • Lastpage
    470
  • Abstract
    Currently, underfill dispense processing is achieved through capillary action, making it a costly and time consuming process. As part of the Low Cost Next Generation Flip Chip Processing Program at Georgia Tech, an advanced flip chip assembly process was developed. This process eliminated the need for time consuming capillary flow processing, and integrates the simultaneous reflow and cure of the solder interconnect and polymer underfill. The advanced process results in a significantly lower assembly cost combined with reduced throughput time. Reduced throughput time and cost were achieved through the compression flow of the underfill material. The flow of the material governs assembly yield and reliability. Flow simulation studies of the placement process were conducted to characterize the compression flow of the underfill and predict void formation. Results yielded design guidelines that gave insight into process parameters such as the limits on underfill print height and underfill viscosity. The results indicated the initial limits of an overall process window for compression flow chip placement
  • Keywords
    compressible flow; encapsulation; finite element analysis; flip-chip devices; flow simulation; integrated circuit manufacture; integrated circuit packaging; microassembling; multichip modules; viscosity; FEM; compression flow chip placement; compression flow modeling; cost reduction; design guidelines; flow simulation; low cost flip chip assembly; placement process; polymer underfill; process parameters; solder interconnect; solder reflow; throughput time reduction; underfill dispense processing; underfill encapsulants; underfill print height limits; underfill viscosity; void formation prediction; Assembly; Conducting materials; Costs; Flip chip; Guidelines; Materials reliability; Polymers; Predictive models; Throughput; Viscosity;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronic Components & Technology Conference, 1998. 48th IEEE
  • Conference_Location
    Seattle, WA
  • ISSN
    0569-5503
  • Print_ISBN
    0-7803-4526-6
  • Type

    conf

  • DOI
    10.1109/ECTC.1998.678735
  • Filename
    678735