Performance Bound Analysis and Retiming of Timed Circuits

Timed asynchronous circuits are efficient in performance and power consumption. Traditional performance analysis method can not analyze timed circuits efficiently. In this paper, we model timed circuits using timed Petri net and digraph. We studied the mean cycle time of timed Petri net model. The upper bound and lower bound of mean cycle time were given. Then we proposed an algorithm for timed circuits retiming. The algorithm can efficiently distribute buffers along communication channels of timed circuits to gain maximal performance and minimal area. These algorithms were applied to phased logic circuitspsila design and optimization.