DocumentCode
1837908
Title
Cleanroom design for Cu-CMP processes
Author
Ishiguro, Takeshi ; Ro, Toshitami
Author_Institution
Takenaka Corp., Chiba, Japan
fYear
2001
fDate
2001
Firstpage
11
Lastpage
14
Abstract
With the progress towards more integrated semiconductor devices and narrower wiring pitches, there has been a shift from aluminum wiring to the use of copper wiring due to its lower electrical resistance. However, the high diffusion coefficient of copper has adverse effects on the device characteristics. There is also some concern that the CMP (chemical mechanical polishing) process used to form copper wiring is a source of chemical contamination in cleanrooms. Experiments have confirmed that the copper contained in the waste fluid produced during wafer polishing is scattered around the inside of the CMP unit. Copper leaking outside the units during maintenance is safely removed by a cleanroom HEPA filter since the copper quickly oxidizes to form particles. However, the copper adheres to the shoes and gloves of the operators who maintain the CMP units and causes cross-contamination to other process areas. Because 300 mm wafers are transported automatically using FOUPs (front-opening unified pods), we anticipate that in future, different processes will be combined in cleanrooms that share the same conventional air-flow space. In this context, cross-contamination from the Cu-CMP process backside can be prevented by segregating the cleanroom so as to isolate the copper process wafer carriers
Keywords
chemical mechanical polishing; clean rooms; copper; impurities; integrated circuit metallisation; surface contamination; 300 mm; Cu; Cu CMP processes; Cu process wafer carriers isolation; Cu wiring; HEPA filter; chemical contamination; chemical mechanical polishing process; cleanroom design; cross-contamination; front-opening unified pods; process areas; semiconductor devices; wafer polishing; waste fluid; wiring pitches; Aluminum; Chemical processes; Contamination; Copper; Electric resistance; Filters; Particle scattering; Process design; Semiconductor devices; Wiring;
fLanguage
English
Publisher
ieee
Conference_Titel
Semiconductor Manufacturing Symposium, 2001 IEEE International
Conference_Location
San Jose, CA
Print_ISBN
0-7803-6731-6
Type
conf
DOI
10.1109/ISSM.2001.962903
Filename
962903
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