GaAs MMIC Probe Measurements and Calibration Techniques

The MMlC designer has several options available to verify the performance and simulation agreement of his circuits. They can be divided into two basic categories: calibration reference plane at the probe tips or on the MMIC chip at the coplanar interface to the device under test (DUT). The calibration technique used determines the reference plane of the measurements. Several on-wafei and off-wafer calibration techniques were used to obtain measurements of GaAs MMICs. A Wafer Probe station and a vector network analyzer were used to obtain LRM, SOLT, and TRL calibrated measurements of GaAs devices. In order to use on wafer calibration, an open, a short, a load, a "short" microstrip line, and a "long" microstrip line were designed and included on the GaAs wafer. An SOLT and a TRL calibration was performed with these on-wafer calibration standards. For off-wafer calibration, the Cascade Microtech Impedance Standard Substrate (ISS) was used to obtain an LRM calibration for a third set of measurements. To equalize the reference plane of the LRM measurements with the on-wafer TRL and SOLT calibration measurements, the MMlC launches which transition from the coplanar probe to the microstrip were subtracted out, i.e. deembeded to equalize the reference plane. A numerical technique was used to extract the approximate s-parameters of the MMIC launch from LRM measured data. Device measurements with all three calibration techniques closely agreed and were repeatable. These deembeded measurements compared favorably to foundry supplied device models.