DocumentCode
1837992
Title
Low power, high speed PLL fabricated in UTSi/sup (R)/ process
Author
Wu, G.C. ; Kelly, D. ; Staab, D. ; Denny, P.
Author_Institution
Peregrine Semicond. Corp., San Diego, CA, USA
fYear
2002
fDate
3-4 June 2002
Firstpage
165
Lastpage
168
Abstract
A CMOS phase locked loop (PLL) design achieves GHz performance, low phase noise, low spurious side-bands and extremely low power (1V, 1GHz, and <1mA of current.) The design is fabricated in 0.5/spl mu/m UTSi/sup (R)/ SOI process which has been previously described [Reedy, 1999].
Keywords
CMOS digital integrated circuits; digital phase locked loops; high-speed integrated circuits; low-power electronics; phase noise; silicon-on-insulator; 0.5 micron; 1 GHz; 1 V; 1 mA; CMOS; SOI process; UTSi process; high speed PLL; low power design; phase noise; spurious side-bands; Batteries; Capacitors; Energy consumption; Frequency; Integrated circuit noise; Inverters; Low voltage; MOSFET circuits; Parasitic capacitance; Phase locked loops;
fLanguage
English
Publisher
ieee
Conference_Titel
Radio Frequency Integrated Circuits (RFIC) Symposium, 2002 IEEE
Conference_Location
Seattle, WA, USA
ISSN
1529-2517
Print_ISBN
0-7803-7246-8
Type
conf
DOI
10.1109/RFIC.2002.1011947
Filename
1011947
Link To Document