A 6.8GHz low-power and low-phase-noise phase-locked loop design

In this paper, we present a technique for low-power and low phase noise phase-locked loop designs. This technique introduces a key parameter, PNUP (phase noise per unit power), to all of the building blocks of a PLL that correlates all the blocks in terms of power and phase noise. By correlating all the independent PLL blocks together, sophisticated PLL design and optimization can be significantly simplified. We demonstrate a 6.8 GHz Frequency synthesizer design in 0.25 um SOI process achieving -108 dBc/Hz phase noise at 100 KHz offset with only 32.75 mW power consumption.