A high-speed variable phase accumulator for an ADPLL architecture

This paper presents a high-speed topology for the variable phase accumulator (VPA) in an all digital phase-locked loop (ADPLL) architecture. The topology increases the speed of the VPA, which is a digital block running at the highest frequency in the ADPLL. The high-speed feature of the topology is achieved by exploiting the fact that the VPA output is used in the reference frequency domain while the circuit needs to handle the RF signal from the ADPLL output. The new topology minimizes the timing critical path and reduces the logic in the highest frequency domain to a shift register. As demonstrated in a 65-nm CMOS process, it allows the VPA to have a speed increase of about 60% without penalty in power dissipation or silicon area.