A new architecture for Cellular Neural Network on reconfigurable hardware with an advance memory allocation method

In this study a discretized version of Cellular Neural Network (CNN) was implemented with an Hardware Description Language using forward Euler approximation. When the designs in literature were reviewed, it was seen that registers of the designs significantly affect occupied chip area. The introduced design is focused on reducing chip area by reducing register occupation while not causing design complexity or lack in processing speed. Block Random Access Memories (Block-RAMs) in Field Programmable Gate Arrays (FPGA) were used instead of register arrays, which were designed to handle the relationship of the neighborhood and input-output communication in previous designs. The proposed design does not require additional memory to store input image and states of the CNN. Storing, reading and updating image, also providing neighbor relations of image were done with the proposed method which includes an advance memory allocation, image partitioning and supplementary blocks for the relationship of the neighborhood. In order to reduce the chip area of Cellular Processors, cellular control was simplified. Cellular Processors which have similar arithmetic units with previous designs occupy less combinatorial part and significantly less registers. The advantage of this design is presented by comparing the proposed designs in literature.