DocumentCode :
1838227
Title :
Simple tool of analysis for cycle time reduction
Author :
Sada, Toshihiro ; Yuen, Ronald A. ; Ichikawa, Masashi ; Yamada, Mamoru ; Kabata, Kazuo
Author_Institution :
NEC Electron., Roseville, CA, USA
fYear :
2001
fDate :
2001
Firstpage :
79
Lastpage :
82
Abstract :
This paper describes a simple and easy to understand technique of achieving cycle time reduction in a semiconductor fab. The technique uses a spreadsheet that calculates theoretical queue time (based on operations research queuing theory) with consideration to the negative effect of very high priority lots ("super hot lots"). The theoretical queue time is compared with actual queue times to identify factory bottlenecks and the best opportunities for cycle time improvement. When this queue time control was introduced, jab cycle time improved 24%
Keywords :
computer aided production planning; integrated circuit manufacture; operations research; production control; queueing theory; actual queue times; average lot model; cycle time reduction; factory bottlenecks; lot transfer time; operations research queuing theory; product planning; queue time control; semiconductor fab; semiconductor industry; spreadsheet; theoretical queue time; very high priority lots; Analytical models; Electronics industry; Job shop scheduling; National electric code; Operations research; Performance analysis; Production facilities; Queueing analysis; Semiconductor device manufacture; Software performance;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Semiconductor Manufacturing Symposium, 2001 IEEE International
Conference_Location :
San Jose, CA
Print_ISBN :
0-7803-6731-6
Type :
conf
DOI :
10.1109/ISSM.2001.962919
Filename :
962919
Link To Document :
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