DocumentCode :
1838321
Title :
Board level reliability of CSP
Author :
Juso, Hiroyuki ; Yamaji, Yasuhisa ; Kimura, Tomoshi ; Fujita, Kazuya ; Kada, Morihiro
Author_Institution :
VLSI Lab., Sharp Corp., Nara, Japan
fYear :
1998
fDate :
25-28 May 1998
Firstpage :
525
Lastpage :
531
Abstract :
Companies are pushing the development of CSP (chip size package or chip scale package), which has almost no limit to LSI chip size. Sharp has developed a CSP, which can be manufactured using existing equipment, and commenced mass production in August 1996. The CSP, a face-up structure on single-sided wiring polyimide substrate, was developed using wire bonding and transfer molding technology, which are proven packaging technologies. Further, the external connection terminals are an area array structure using solder balls, with a pitch of 0.8-1.0 mm. The area array package, which has a structure using solder balls or “bumps” as external connection terminals similar to Sharp´s CSP, is different from current flat type plastic packages (SOP (small outline package), QFP (quad flat package), etc.) in that the mechanism of stress on the solder connectors being reduced due to the lead frame does not operate. For that reason, after mounting on the motherboard, heat or mechanical stress can be expected to concentrate in the solder connections, and there is some concern that this reduces the post-mounting reliability. The factors that are believed to affect CSP reliability after mounting are the CSP´s outline size, structure, and material, the motherboard´s material, design, and manufacturing methods, etc. Sharp conducted a temperature cycle test similar to those currently performed to evaluate resistance to heat stress. For resistance to mechanical stress. Sharp also conducted bending and drop impact tests on a mounted motherboard under various conditions
Keywords :
integrated circuit packaging; integrated circuit reliability; large scale integration; lead bonding; life testing; 0.8 to 1.0 mm; CSP; LSI chip size; Sharp; area array structure; bending tests; board level reliability; chip scale package; chip size package; drop impact tests; face-up structure; post-mounting reliability; single-sided wiring polyimide substrate; solder balls; solder connections; temperature cycle test; transfer molding technology; wire bonding; Chip scale packaging; Conducting materials; Large scale integration; Manufacturing; Mass production; Packaging machines; Plastic packaging; Stress; Testing; Wiring;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic Components & Technology Conference, 1998. 48th IEEE
Conference_Location :
Seattle, WA
ISSN :
0569-5503
Print_ISBN :
0-7803-4526-6
Type :
conf
DOI :
10.1109/ECTC.1998.678743
Filename :
678743
Link To Document :
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