DocumentCode
1838379
Title
Arithmetic module generator with algorithm optimization capability
Author
Watanabe, Yuki ; Homma, Naofumi ; Aoki, Takafumi ; Higuchi, Tatsuo
Author_Institution
Grad. Sch. of Inf. Sci., Tohoku Univ., Sendai
fYear
2008
fDate
18-21 May 2008
Firstpage
1796
Lastpage
1799
Abstract
This paper presents an arithmetic module generator based on an arithmetic description language called ARITH. The use of ARITH makes it possible to describe a wide variety of arithmetic algorithms in a unified manner. The ARITH descriptions are formally verified in the generator even if the arithmetic algorithms include unconventional number systems for operands or internal variables. The proposed generator also optimizes arithmetic algorithms by using performance profiles derived from the previous generation. From these features, we can obtain high-performance arithmetic modules whose functions are completely verified at the algorithm level. In this paper, we demonstrate that the optimal prefix adders improved the performance of generated arithmetic modules such as multipliers in comparison with the standard prefix adders.
Keywords
adders; digital arithmetic; optimisation; ARITH; algorithm optimization capability; arithmetic description language; arithmetic module generator; optimal prefix adders; prefix adders; Adders; Application software; DH-HEMTs; Data structures; Digital arithmetic; Formal verification; Hardware design languages; Libraries; Logic circuits; Signal processing algorithms;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on
Conference_Location
Seattle, WA
Print_ISBN
978-1-4244-1683-7
Electronic_ISBN
978-1-4244-1684-4
Type
conf
DOI
10.1109/ISCAS.2008.4541788
Filename
4541788
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