DocumentCode
1838385
Title
Reconciling high-speed scheduling with dispatching in wafer fabs
Author
Johnston, Mark D.
Author_Institution
PRI Automation/Interval Logic Corp., Moutain View, CA, USA
fYear
2001
fDate
2001
Firstpage
107
Lastpage
110
Abstract
A novel approach to reconciling global optimizing scheduling with real-time dispatching is presented. High speed scheduling is accomplished by two simultaneous cooperating scheduling processes, one of which generates longer term schedules while the other is focused with higher resolution on the nearer term. Real-time dispatching is based on the most recently generated near term schedule, carefully reconciled with events that could affect its current validity on the shopfloor. Results are presented which show a fivefold performance speedup in schedule generation time, as well as significant schedule quality improvements over pure dispatching approaches
Keywords
dispatching; integrated circuit manufacture; production control; production engineering computing; dual span scheduling; global optimizing scheduling; high speed scheduling; performance speedup; real-time dispatching; schedule generation time; schedule quality improvements; semiconductor wafer fabs; shopfloor; Automatic control; Automation; Control systems; Convergence; Dispatching; Job shop scheduling; Logic; Manufacturing processes; Productivity; Semiconductor device manufacture;
fLanguage
English
Publisher
ieee
Conference_Titel
Semiconductor Manufacturing Symposium, 2001 IEEE International
Conference_Location
San Jose, CA
Print_ISBN
0-7803-6731-6
Type
conf
DOI
10.1109/ISSM.2001.962926
Filename
962926
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