Author :
Fukasawa, M. ; Lane, S. ; Angyal, M. ; Chand, K. ; Chen, F. ; Christiansen, C. ; Fitzsimmons, J. ; Gill, J. ; Ida, K. ; Inoue, K. ; Kumar, K. ; Li, B. ; McLaughlin, Paul ; Melville, I. ; Minami, M. ; Nguyen, S. ; Penny, C. ; Sakamoto, A. ; Shimooka, Y. ;
Abstract :
This paper describes a comprehensive characterization of a 65 nm, 300 mm wafer size interconnect technology with SiCOH material (k=2.8). Excellent film properties of the SiCOH material and precise process optimization enable the minimization of layer damage during etching and strip processes. 3D modeling reveals that the k-value of the SiCOH material was maintained at its initial value after the integration. Electrical yield, reliability and chip-to-package (CPI) evaluation are also presented. The results were comparable with the conventional SiCOH integration scheme.
Keywords :
copper; dielectric thin films; etching; integrated circuit interconnections; integrated circuit modelling; integrated circuit reliability; integrated circuit yield; silicon compounds; 300 mm; 3D modeling; 65 nm; BEOL process integration; Cu-SiCOH; chip-to-package evaluation; electrical yield; etching; layer damage minimization; low-k interconnects; process optimization; reliability; strip process; Adhesives; Bonding; Etching; LAN interconnection; Microelectronics; Oxygen; Semiconductor materials; Strips; Thermal stresses; Wiring;
