• DocumentCode
    1838569
  • Title

    45 nm-node BEOL integration featuring porous-ultra-low-k/Cu multilevel interconnects

  • Author

    Sugiura, I. ; Nakata, Y. ; Misawa, N. ; Otsuka, S. ; Nishikawa, N. ; Iba, Y. ; Sugimoto, Futoshi ; Setta, Y. ; Sakai, H. ; Mizushima, Y. ; Kotaka, Y. ; Uchibori, C. ; Suzuki, T. ; Kitada, H. ; Koura, Y. ; Nakano ; Karasawa, T. ; Ohkura ; Watatani, H. ; Sa

  • Author_Institution
    Fujitsu Ltd., Tokyo, Japan
  • fYear
    2005
  • fDate
    6-8 June 2005
  • Firstpage
    15
  • Lastpage
    17
  • Abstract
    45 nm-node multilevel Cu interconnects with porous-ultra-low-k have successfully been integrated. Key features to realize 45 nm-node interconnects are as follows: 1) porous ultra-low-k material NCS (nano-clustering silica) has been applied to both wire-level and via-level dielectrics (what we call full-NCS structure), and its sufficient robustness has been demonstrated; 2) 70-nm vias have been formed by high-NA 193 nm lithography with fine-tuned model-based OPC and multi-hard-mask dual-damascene process - more than 90% yields of 1 M via chains have been obtained; 3) good TDDB (time-dependent dielectric breakdown) characteristics of 70 nm wire spacing filled with NCS has been achieved. Because it is considered that the applied-voltage (Vdd) of a 45 nm-node technology will be almost the same as that of the previous technology, the dielectrics have to endure the high electrical field. NCS in Cu wiring has excellent insulating properties without any pore sealing materials which cause either the keff value or actual wire width to be worse.
  • Keywords
    copper; dielectric thin films; electric breakdown; integrated circuit interconnections; nanoporous materials; silicon compounds; ultraviolet lithography; 193 nm; 45 nm; 70 nm; BEOL integration; Cu-SiO2; OPC; TDDB; applied voltage induced high electrical field; full-NCS structure; high-NA UV lithography; multilevel interconnects; multiple-hard-mask dual-damascene process; nanoclustering silica; porous-ultra-low-k materials; time-dependent dielectric breakdown; via-level dielectrics; wire-level dielectrics; Cable insulation; Dielectric breakdown; Dielectric materials; Dielectrics and electrical insulation; Lithography; Nanostructured materials; Robustness; Silicon compounds; Wire; Wiring;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Interconnect Technology Conference, 2005. Proceedings of the IEEE 2005 International
  • Print_ISBN
    0-7803-8752-X
  • Type

    conf

  • DOI
    10.1109/IITC.2005.1499906
  • Filename
    1499906