Author :
Ishii, A. ; Matsumoto, S. ; Hattori, T. ; Suzuki, S. ; Isono, S. ; Iwasaki, A. ; Tomita, K. ; Hashimoto, K. ; Tawa, S. ; Furusawa, T. ; Kodama, D. ; Ogawa, S. ; Suzumura, S. ; Tsutsue, M. ; Goto, K. ; Kobayashi, K. ; Ohshita, H. ; Hamada, M. ; Amoh, N. ;
Abstract :
Interface engineering technologies are developed for highly-reliable 65 nm-node Cu/low-k interconnect integration using a ULK dielectric (k=2.6) in a hybrid ILD structure. For electromigration (EM) reliability, the mechanical integrity at the SiOC/SiC(N,O) interface exposed on the via sidewalls is found to be critical. For TDDB reliability, reduction in Cu-containing defects at the SiC(N,O)/SiOC interface at the top of the metal line is critical. By optimizing these interfaces, the EM and the TDDB lifetimes are significantly improved.
Keywords :
dielectric thin films; electric breakdown; electromigration; integrated circuit interconnections; integrated circuit reliability; mechanical strength; 65 nm; Cu; SiCN-SiOC; TDDB reliability; ULK dielectric; electromigration reliability; exposed via sidewall mechanical integrity; hybrid ILD structure; interconnect integration reliability; interface engineering; Degradation; Dielectrics; Geometry; Large scale integration; Manufacturing industries; Manufacturing processes; Reliability engineering; Semiconductor device manufacture; Testing; Ultra large scale integration;
