DocumentCode
1838668
Title
ESD protection of RF circuits in standard CMOS process
Author
Higashi, K. ; Adan, A.O. ; Fukumi, M. ; Tanba, N. ; Yoshimasu, T. ; Hayashi, M.
Author_Institution
IC Dev. Group, Sharp Corp., Tenri, Japan
fYear
2002
fDate
3-4 June 2002
Firstpage
285
Lastpage
288
Abstract
The tradeoffs in the ESD protection device for RFCMOS circuits are described, and the characteristics of an SCR-based ESD structure are presented. The parasitic capacitance of the ESD structure is reduced to /spl sim/150 fF. 3 kV HBM and 750 V CDM are achieved in a LNA working at 2.5 GHz with NF<4dB, applicable for Bluetooth wireless transceiver.
Keywords
CMOS analogue integrated circuits; UHF amplifiers; UHF integrated circuits; electrostatic discharge; thyristor circuits; transceivers; wireless LAN; 150 fF; 2.5 GHz; 3 kV; 750 V; Bluetooth wireless transceiver; ESD intrinsic characteristics; ESD protection device; HBM; LNA; RF CMOS circuits; SCR-based structure; charged device model; device tradeoffs; parasitic capacitance; trigger diode; Analog integrated circuits; CMOS process; Diodes; Electrostatic discharge; Parasitic capacitance; Protection; Radio frequency; Radiofrequency integrated circuits; Thyristors; Transceivers;
fLanguage
English
Publisher
ieee
Conference_Titel
Radio Frequency Integrated Circuits (RFIC) Symposium, 2002 IEEE
Conference_Location
Seattle, WA, USA
ISSN
1529-2517
Print_ISBN
0-7803-7246-8
Type
conf
DOI
10.1109/RFIC.2002.1012050
Filename
1012050
Link To Document