Latch-up characterization in standard and twin-tub test structures by electrical measurements, 2-D simulations and IR microscopy

Author

Cavioni, Tiziana ; Cecchetti, Massimo ; Muschitiello, Michele ; Spiazzi, Giorgio ; Vottre, Ireneo ; Zanoni, Enrico

Author_Institution

SGS Thomson, Milano, Italy

fYear

1990

fDate

5-7 March 1990

Firstpage

41

Lastpage

46

Abstract

The influence of different layout parameters on latchup susceptibility was studied on standard four-stripes test structures fabricated using two bulk processes: standard n-well and a twin-tub technology. Twin-tub structures show increased latchup hardness and guard-ring effectiveness, mainly due to the increased doping level and the consequent decrease in substrate and well resistances. Standard and twin-tub structures show marked three-dimensional effects in the holding characteristics, which lead to an uneven distribution of the latchup current within test structures and hysteresis in the I-V characteristics.<>

Keywords

CMOS integrated circuits; digital simulation; infrared imaging; integrated circuit technology; integrated circuit testing; optical microscopy; reliability; 2-D simulations; CMOS; I-V characteristics; IR microscopy; bulk processes; electrical measurements; guard-ring effectiveness; holding characteristics; hysteresis; increased doping level; latchup characterisation test structures; latchup hardness; latchup susceptibility; layout parameters; standard four-stripes test structures; three-dimensional effects; twin-tub test structures; CMOS technology; Circuit testing; Electric variables measurement; MOS devices; Measurement standards; Microscopy; Research and development; Standards development; Substrates; Surface resistance;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronic Test Structures, 1990. ICMTS 1990. Proceedings of the 1990 International Conference on

Conference_Location

San Diego, CA, USA

Type

conf

DOI

10.1109/ICMTS.1990.67877

Filename

67877