Title :
A method of test pattern generation for multiple-valued PLAs
Author :
Nagata, Yasunori ; Afuso, Chushin
Author_Institution :
Dept. of Electr. Eng., Univ. of the Ryukyus, Okinawa, Japan
Abstract :
An easy test pattern generation (ETPG) method is developed for multiple-valued programmable logic arrays (MV PLAs). The ETPG so generated can detect crosspoint faults, weight faults, and their fault positions. In comparison with binary ETPG, it is shown that the number of test vectors does not increase as fast as the radix number of multiple-valued functions increases. The ETPG method for a product line is generalized for a total PLA testing algorithm
Keywords :
fault location; logic arrays; logic testing; many-valued logics; crosspoint faults; easy test pattern generation; fault positions; multiple-valued programmable logic arrays; product line; radix number; test pattern generation; test vectors; weight faults; Charge coupled devices; Charge-coupled image sensors; Fault detection; Hybrid power systems; Logic testing; Programmable logic arrays; Silicon; Test pattern generators; Very large scale integration; Voltage;
Conference_Titel :
Multiple-Valued Logic, 1993., Proceedings of The Twenty-Third International Symposium on
Conference_Location :
Sacramento, CA
Print_ISBN :
0-8186-3350-6
DOI :
10.1109/ISMVL.1993.289576
