Title :
A robust high voltage Si LDMOS model extraction process to achieve first pass linear RFIC amplifier design success
Author :
Pla, J.A. ; Bridges, D.
Author_Institution :
Semicond. Products Sector, Motorola Inc., Tempe, AZ, USA
Abstract :
A robust model extraction procedure was developed for a high voltage Si LDMOS RFIC process to achieve first pass linear RFIC amplifier design success. The model extraction process utilizes pulsed isothermal small-signal S-parameter measurements and extracted large-signal Root Models at three different temperatures to extract model parameters for Motorola´s Electro-Thermal (MET) FET analytical model. Large-signal model validation was performed against loadpull measurements under 1-tone and 2-tone stimuli. Also, the models were developed into a design kit within Agilent/sup (R)/ EEsof/sup (R)/´s ADS/sup (R)/ (Advanced Design System) to design a wide-band 30 Watt power amplifier IC which achieved first pass design success.
Keywords :
MMIC power amplifiers; MOS analogue integrated circuits; S-parameters; circuit CAD; circuit optimisation; elemental semiconductors; equivalent circuits; field effect MMIC; integrated circuit modelling; power integrated circuits; silicon; wideband amplifiers; Si; design kit; first pass design success; high voltage LDMOS RFIC; large-signal Root Models; large-signal model validation; linear RFIC amplifier; loadpull measurements; nonlinear transistor models; pulsed isothermal small-signal S-parameter; robust model extraction procedure; two step global optimization; wideband power amplifier IC; Integrated circuit modeling; Isothermal processes; Power system modeling; Pulse amplifiers; Pulse measurements; Radiofrequency integrated circuits; Robustness; Scattering parameters; Temperature; Voltage;
Conference_Titel :
Radio Frequency Integrated Circuits (RFIC) Symposium, 2002 IEEE
Conference_Location :
Seattle, WA, USA
Print_ISBN :
0-7803-7246-8
DOI :
10.1109/RFIC.2002.1012064
