A new test structure to characterize the latchup effect

Author

Cané, C. ; Lozano, M. ; Cabruja, E. ; Lora-Tamayo, E. ; Serra-Mestres, F.

Author_Institution

Centre Nacional de Microelectron., Barcelona, Spain

fYear

1990

fDate

5-7 March 1990

Firstpage

47

Lastpage

50

Abstract

A test structure for easily determining the sensitivity of different geometries and technological options to latchup is presented. The circuit is an astable oscillator composed of a p-n-p-n device with an integrated resistor and capacitor. It is used to obtain fast and comparative results with very simple instrumentation. Test structures are designed and produced with a 5- mu m CMOS process, although they are specially suited for VLSI technologies. Experimental results give very good agreement with other latchup test procedures. Much more accuracy can be obtained with a simple digital oscilloscope.<>

Keywords

CMOS integrated circuits; VLSI; integrated circuit technology; integrated circuit testing; 5 micron; CMOS process; VLSI; astable oscillator; digital oscilloscope; geometrical options; integrated resistor and capacitor; latchup characterisation test structures; latchup effect; latchup sensitivities; latchup test procedures; p-n-p-n device; simple instrumentation; technological options; test structure; CMOS process; CMOS technology; Capacitors; Circuit testing; Geometry; Instruments; Integrated circuit technology; Oscillators; Resistors; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronic Test Structures, 1990. ICMTS 1990. Proceedings of the 1990 International Conference on

Conference_Location

San Diego, CA, USA

Type

conf

DOI

10.1109/ICMTS.1990.67878

Filename

67878