LSP speech synthesis ASIC architecture

Author

Wu, Xingjun ; Sun, Yihe

Author_Institution

Inst. of Microelectron., Tsinghua Univ., Beijing, China

fYear

1995

fDate

24-28 Oct 1995

Firstpage

700

Lastpage

702

Abstract

A speech synthesis ASIC based on the line spectrum pair (LSP) scheme has been designed. In this ASIC, we encoded the LSP parameters with 4-bit Differential Quantization, and designed a two´s complement 12-bit fixed-point serial pipeline arithmetic operations with rounding to perform the operations of the LSP speech synthesis digital filter. Finally, we verified our design for Chinese single-syllable pronunciations and continuous speech using FPGA, and obtained good synthetic speech at low bit rate (about 2.2 kbps)

Keywords

application specific integrated circuits; digital arithmetic; digital filters; field programmable gate arrays; pipeline arithmetic; quantisation (signal); speech synthesis; 2.2 kbit/s; 4-bit differential quantization; Chinese single-syllable pronunciations; FPGA; LSP parameter encoding; continuous speech; line spectrum pair scheme; low bit rate; speech synthesis ASIC architecture; speech synthesis digital filter; two´s complement 12-bit fixed-point serial pipeline arithmetic operations; Application specific integrated circuits; Bit rate; Digital arithmetic; Digital filters; Frequency; Pulse generation; Quantization; Sampling methods; Speech synthesis; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology, 1995 4th International Conference on

Conference_Location

Beijing

Print_ISBN

0-7803-3062-5

Type

conf

DOI

10.1109/ICSICT.1995.503532

Filename

503532