Multiple-valued PLA minimization by concurrent multiple and mixed simulated annealing

Simulated annealing applied to multiple-valued programmable logic array (MVL PLA) design is analyzed. Of specific interest is the use of parallel processors. The use of loosely coupled, coarse-grained parallel systems is considered, and the relationship between the quality of the solution and computation time, on the one hand and simulated annealing parameters (start temperature, cooling rate, etc.) on the other is studied. Simulated annealing is also investigated in the case in which there is a mixture of move types. The mixed-move approach provides improvement in both the number of product terms and computation time