Title :
Multiple-valued PLA minimization by concurrent multiple and mixed simulated annealing
Author :
Yildirim, Cem ; Butler, Jon T. ; Yang, Chyan
Author_Institution :
Dept. of Electr. & Comput. Eng., US Naval Postgraduate Sch., Monterey, CA, USA
Abstract :
Simulated annealing applied to multiple-valued programmable logic array (MVL PLA) design is analyzed. Of specific interest is the use of parallel processors. The use of loosely coupled, coarse-grained parallel systems is considered, and the relationship between the quality of the solution and computation time, on the one hand and simulated annealing parameters (start temperature, cooling rate, etc.) on the other is studied. Simulated annealing is also investigated in the case in which there is a mixture of move types. The mixed-move approach provides improvement in both the number of product terms and computation time
Keywords :
logic arrays; logic design; many-valued logics; simulated annealing; PLA minimization; coarse-grained parallel systems; concurrent multiple simulated annealing; mixed simulated annealing; multiple-valued programmable logic array; Analytical models; Computational modeling; Cooling; Cost function; Laboratories; Logic design; Minimization methods; Programmable logic arrays; Simulated annealing; Temperature;
Conference_Titel :
Multiple-Valued Logic, 1993., Proceedings of The Twenty-Third International Symposium on
Conference_Location :
Sacramento, CA
Print_ISBN :
0-8186-3350-6
DOI :
10.1109/ISMVL.1993.289587
