DocumentCode
1839280
Title
Fast synthesis for ternary Reed-Muller expansion
Author
Hong, Qinhua ; Fei, Benchu ; Wu, Haomin ; Perkowski, Marek A. ; Zhuang, Nan
Author_Institution
Dept. of Math., Ningbo Univ., Zhejiang, China
fYear
1993
fDate
24-27 May 1993
Firstpage
14
Lastpage
16
Abstract
A direct algorithm for calculating Reed-Muller coefficients under each fixed polarity is derived. This algorithm has not only a simple procedure but also much lower computational cost than the step-by-step flow graph algorithm with the polarities in Gray code order of D.H. Green (1989). Therefore, it lends itself to fast parallel computation
Keywords
logic design; ternary logic; Gray code order; direct algorithm; fast parallel computation; ternary Reed-Muller expansion; Circuit synthesis; Circuit testing; Computational efficiency; Reflective binary codes;
fLanguage
English
Publisher
ieee
Conference_Titel
Multiple-Valued Logic, 1993., Proceedings of The Twenty-Third International Symposium on
Conference_Location
Sacramento, CA
Print_ISBN
0-8186-3350-6
Type
conf
DOI
10.1109/ISMVL.1993.289588
Filename
289588
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