Spiral inductor performance in deep-submicron bulk-CMOS with copper interconnects

Author

Kuhn, W.B. ; Orsborn, A.W. ; Peterson, M.C. ; Kythakyapuzha, S.R. ; Hussein, Ahmed I. ; Jun Zhang ; Jianming Li ; Shumaker, E.A. ; Nair, N.C.

Author_Institution

Dept. of Electr. & Comput. Eng., Kansas State Univ., Manhattan, KS, USA

fYear

2002

fDate

3-4 June 2002

Firstpage

385

Lastpage

388

Abstract

This paper reviews design considerations for spiral inductors in bulk CMOS and reports investigations carried out in a commercial 0.18 /spl mu/m process using 6-layer copper metallization. Quality factors of approximately 8 are measured for 10 nH spirals operating between 1 and 2 GHz. Comparisons of Q and self-resonant frequency are provided for a variety of construction variables including with/without a patterned ground shield, metal-6 only versus stacking layers 3 thru 6, dense versus sparse vias, wide versus narrow traces, and with/without metal-fill.

Keywords

CMOS integrated circuits; Q-factor; eddy currents; field effect MMIC; inductors; integrated circuit interconnections; integrated circuit metallisation; 1 to 2 GHz; copper interconnects; deep-submicron bulk CMOS; design considerations; inductance; metal-fill; narrow traces; optimization; patterned ground shield; quality factors; self-resonant frequency; spiral inductors; wide traces; CMOS process; Copper; Eddy currents; Frequency; Inductance; Inductors; Modems; Q factor; Spirals; Stacking;

fLanguage

English

Publisher

ieee

Conference_Titel

Radio Frequency Integrated Circuits (RFIC) Symposium, 2002 IEEE

Conference_Location

Seattle, WA, USA

ISSN

1529-2517

Print_ISBN

0-7803-7246-8

Type

conf

DOI

10.1109/RFIC.2002.1012073

Filename

1012073