DocumentCode :
1839412
Title :
Geometry and bias current optimization for SiGe HBT cascode low-noise amplifiers
Author :
Qingqing Liang ; Guofu Niu ; Cressler, J.D. ; Taylor, S. ; Harame, D.L.
Author_Institution :
Electr. & Comput. Eng. Dept., Auburn Univ., AL, USA
fYear :
2002
fDate :
3-4 June 2002
Firstpage :
407
Lastpage :
410
Abstract :
This work presents a new design methodology for inductively-degenerated cascode low-noise amplifiers using advanced epitaxial-base SiGe HBTs. Noise figure, gain, and IIP3 are calculated using calibrated linear circuit analysis and a Volterra series methodology as a function of the two major design variables: emitter geometry and biasing current. An optimum SiGe HBT LNA design point which balances input impedance match, high IIP3, noise figure, gain, and power consumption is obtained from calculated noise figure, gain, and IIP3 contours as a function of bias current and geometry. Simplified analytical expressions of IIP3, gain, and noise figure are presented to give additional insight. The optimum LNA design point for the 50 GHz SiGe HBT process technology under study yields a 2 GHz LNA with 15.8 dBm IIP3, 18 dB gain, 1.15 dB noise figure, and a |s11| less than -20 dB for a biasing current of 7.5 mA. The calculated results show good agreement with HP Advanced-Design-System simulations. The design tradeoffs illuminated by this optimization methodology are highlighted and discussed.
Keywords :
Ge-Si alloys; UHF amplifiers; UHF integrated circuits; Volterra series; bipolar analogue integrated circuits; circuit optimisation; heterojunction bipolar transistors; integrated circuit design; integrated circuit noise; linear network analysis; linear network synthesis; semiconductor materials; 1.15 dB; 18 dB; 2 GHz; 7.5 mA; IIP3; SiGe; Volterra series methodology; advanced epitaxial-base SiGe HBTs; biasing current; calibrated linear circuit analysis; design methodology; design tradeoffs; design variables; emitter geometry; gain; inductively-degenerated cascode LNA; input impedance match; low-noise amplifiers; noise figure; optimization methodology; optimum SiGe HBT LNA design; power consumption; Circuit analysis; Design methodology; Geometry; Germanium silicon alloys; Heterojunction bipolar transistors; Impedance; Linear circuits; Low-noise amplifiers; Noise figure; Silicon germanium;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Radio Frequency Integrated Circuits (RFIC) Symposium, 2002 IEEE
Conference_Location :
Seattle, WA, USA
ISSN :
1529-2517
Print_ISBN :
0-7803-7246-8
Type :
conf
DOI :
10.1109/RFIC.2002.1012078
Filename :
1012078
Link To Document :
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