0.18um CMOS integrated chipset for 5.8GHz DSRC systems with +10dBm output power

This paper describes a radio architecture and circuit implementation results for Korea/Japan standards of 5.8 GHz DSRC systems. By characterizing specific system features concerning practical environments such as communication cell area and in-vehicle temperature, we extract detailed design specifications and show a practical system implementation. Also, we introduce a new receiver sensitivity control method which has superior signal quality over the conventional ones by gating the detected RX data with respect to the received RSSI, without degradation of receiver SNR. When the complete transceiver circuit is integrated on a chip using 0.18 mum CMOS technology, the transmitter carries up to +10.5 dBm of output power and the receiver has less than 17 dB of system noise figure. The active current consumptions are 102 mA and 52 mA during TX- and RX- modes, respectively, for 1.8V supply voltage.