DocumentCode
1839567
Title
The execution of aggressive PBGA substrate yield learning in an existing PWB facility
Author
Fuller, James W., Jr. ; Norton, Elizabeth M.
Author_Institution
IBM Corp., USA
fYear
1998
fDate
25-28 May 1998
Firstpage
834
Lastpage
837
Abstract
As the market for PBGA products explodes and substrate facilities are designed, built, and brought on line, yield learning is vitally important. It is rare that a new product will be introduced at its steady state yield target, necessitating aggressive yield improvement planning. In particular, manufacturers who have converted portions of existing PWB capacity to PBGA product sets will find this to be true. In this paper, the authors articulate the significant challenges manufacturers face ramping up PBGA product. Complex logistics, multiple process flows, multiple customer requirements, aggressive delivery schedules, non-PWB defect mechanisms, non-functionally defined engineering specifications, and a paradigm shift in manufacturing philosophy complicate a product with great intrinsic manufacturing difficulty. This paper reviews in detail the challenges, philosophy and methodology employed to achieve dramatic improvement in PBGA product yields. The paper also includes suggestions for changes in business process procedures to ensure yield learning is engrained as part of any PBGA product introduction. A detailed system of matrix management that utilized process control as the foundation for yield improvement is included. The organization structure, review cycle, improvement road maps, yield tracking and data analysis are discussed in detail. Overall yield improvement results, along with several representative products, are generically shared to validate the philosophy and methodology employed
Keywords
integrated circuit packaging; integrated circuit yield; management; production; substrates; PBGA substrate yield learning; PWB facility; aggressive yield improvement planning; business process procedures; complex logistics; delivery schedules; manufacture; matrix management; multiple customer requirements; multiple process flows; nonPWB defect mechanisms; nonfunctionally defined engineering specifications; Capacity planning; Gold; Manufacturing processes; Microelectronics; Packaging; Process control; Pulp manufacturing; Random access memory; Steady-state; Substrates;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronic Components & Technology Conference, 1998. 48th IEEE
Conference_Location
Seattle, WA
ISSN
0569-5503
Print_ISBN
0-7803-4526-6
Type
conf
DOI
10.1109/ECTC.1998.678804
Filename
678804
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