DocumentCode
1839700
Title
Logic synthesis method for FPGAs with embedded memory blocks
Author
Rawski, Mariusz ; Falkowski, Bogdan J. ; Luba, Tadeusz
Author_Institution
Inst. of Telecommun., Warsaw Univ. of Technol., Warsaw
fYear
2008
fDate
18-21 May 2008
Firstpage
2014
Lastpage
2017
Abstract
The paper presents a logic synthesis method oriented towards FPGA architectures with specialized embedded memory blocks. Existing methods do not ensure effective utilization of possibilities provided by these specialized embedded modules. The presented method, based on balanced decomposition, leads to much more effective implementations of digital systems in modern FPGA structures.
Keywords
embedded systems; field programmable gate arrays; network synthesis; FPGA architectures; balanced decomposition; digital systems; embedded memory blocks; embedded modules; logic synthesis method; Design automation; Digital systems; Field programmable gate arrays; Finite impulse response filter; Input variables; Logic design; Logic devices; Paper technology; Programmable logic arrays; Random access memory;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on
Conference_Location
Seattle, WA
Print_ISBN
978-1-4244-1683-7
Electronic_ISBN
978-1-4244-1684-4
Type
conf
DOI
10.1109/ISCAS.2008.4541842
Filename
4541842
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