Title :
Co-evolutionary reliability-oriented high-level synthesis
Author_Institution :
Electr. & Comput. Eng. Sch., Univ. of Tehran, Tehran
Abstract :
The main contribution of this paper is utilizing bio- inspired evolutionary algorithm for reliability oriented high level synthesis. In this paper genetic algorithm is used to schedule a data-flow graph considering latency and resource allocation considering resource constraints and area overhead. Then a co-evolutionary strategy merges the results of these solutions to find the RT level design of the circuit which satisfies both performance and area constraints. To satisfy the user- defined reliability, another genetic algorithm is developed to insert some hardware redundancies to the resulted data-path. Experimental results show using the proposed approach results in an acceptable reliability with a considerable area reduction in comparison with TMR.
Keywords :
data flow graphs; genetic algorithms; high level synthesis; reliability; bio-inspired evolutionary algorithm; data-flow graph; genetic algorithm; reliability-oriented high level synthesis; Circuit synthesis; Circuit testing; Combinational circuits; Delay; Evolutionary computation; Genetic algorithms; High level synthesis; Redundancy; Reliability engineering; Very large scale integration;
Conference_Titel :
Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on
Conference_Location :
Seattle, WA
Print_ISBN :
978-1-4244-1683-7
Electronic_ISBN :
978-1-4244-1684-4
DOI :
10.1109/ISCAS.2008.4541845