A study on ILD process of simple and CMP skip using polysilazane-based SOG

Author

Lee, Jung-Ho ; Choi, Jung-Sik ; Lee, Dong-Jun ; Chon, Sang-Moon ; Hwang, Sun-Sam ; Cho, Sang-Deog

Author_Institution

Kiheung Plant, Samsung Electron. Co. Ltd., Kyunggi, South Korea

fYear

2001

fDate

2001

Firstpage

317

Lastpage

320

Abstract

Unit process conditions including coating and baking were optimized to use polysilazane-based spin on glass(SZ-SOG) which has excellent gap filling and planarization ability in an inter layer dielectric (ILD) layer, and this material was successfully and simply integrated for the first time in an ILD layer of a logic device without an expensive chemical mechanical polishing (CMP) process. Device characteristics showed that breakdown voltage and transistor threshold voltage of devices with SZ-SOG in the ILD layer are comparable with those with the conventional borophosphosilicate glass (BPSG). Also, the yield results showed that SZ-SOG group without CMP is similar to BPSG group with CMP. SZ-SOG has no reliability problems even up to 1000 hr

Keywords

dielectric thin films; etching; integrated circuit reliability; integrated circuit yield; semiconductor device breakdown; silicon compounds; spin coating; surface hardening; 0 to 1000 hr; ILD process; SiO₂; baking; breakdown voltage; coating; gap filling ability; inter layer dielectric; planarization ability; polysilazane-based SOG; reliability; spin on glass; transistor threshold voltage; yield results; Business; Coatings; Dielectric devices; Filling; Large scale integration; Logic devices; Materials science and technology; Optical films; Planarization; Semiconductor films;

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Manufacturing Symposium, 2001 IEEE International

Conference_Location

San Jose, CA

Print_ISBN

0-7803-6731-6

Type

conf

DOI

10.1109/ISSM.2001.962976

Filename

962976