Author :
Yang, C.-C. ; Edelstein, D. ; Clevenger, L. ; Cowley, A. ; Gill, Jaswinder ; Chanda, K. ; Simon, A. ; Dalton ; Agarwala, B. ; Cooney, E. ; Nguyen, D. ; Spooner, T. ; Stamper, A.
Author_Institution :
Dev. Center, IBM Semicond. Res., Hopewell Junction, NY, USA
Abstract :
The paper describes a new physical vapor deposition (PVD) metallization scheme that shows a better extendibility for future technology nodes as compared to the conventional scheme. In addition to reducing the thicknesses of both the diffusion barrier and the copper seed layer (Yang, C.-C. et al., MRS Adv. Metallization Conf., p.213, 2004), this new scheme also features a sacrificial process (also called barrier-first process) (Alers, G., IEEE Int. Interconnect Technology Conf., 2003), a via-punch through process (Edelstein, D. et al., IEEE Int. Reliability Physics Symp., p.316, 2004; Kuma, N. et al., MRS Adv. Metallization Conf, p.247, 2004) and a simultaneous preclean with a metal neutral deposition process (Yang et al., US Patent 6,784,105, 2004; Uzoh, C. et al., US Patents 5,930,669, 1999; 5,933,753, 1999; 6,429,519, 2002). Significant metal line and via contact resistance decrease was observed with equal or better reliability. The impact of a sputter etch integration scheme on electrical yield and reliability is also reported. The new sputter scheme decreases contact resistance at the via/interconnect interface and can offset the one resulting from dimension scaling and thus extends PVD metallization usefulness for future technologies.
Keywords :
contact resistance; copper; diffusion barriers; integrated circuit interconnections; integrated circuit metallisation; integrated circuit reliability; integrated circuit yield; sputter etching; vapour deposition; Cu; PVD barrier/seed; PVD metallization; back-end of line copper metallization; barrier-first process; contact resistance; copper seed layer; diffusion barrier; metal line resistance; metal neutral deposition process; physical vapor deposition metallization scheme; reliability; sacrificial process; sputter etch integration scheme; via contact resistance; via-punch through process; yield; Argon; Atherosclerosis; Contact resistance; Copper; Dielectrics; Glass; Integrated circuit interconnections; Maintenance; Metallization; Sputter etching;