Title :
The J-Machine architecture and evaluation
Author :
Dally, W.J. ; Keen, J.S. ; Noakes, M.D.
Author_Institution :
MIT, Cambridge, MA, USA
Abstract :
The authors discuss the architecture of the J-Machine and evaluate the effectiveness of the mechanisms embodied in the message-driven processor (MDP). The J-Machine is a fine-grained distributed memory multicomputer that provides low-overhead mechanisms for general-purpose parallel computing. Each processing node consists of an MDP and 1 Mbyte of DRAM. The MDP microprocessor integrates communication, computation, and memory management functions in a single VLSI chip. A 512-node J-Machine is operational and is due to be expanded to 1024 nodes in January 1993.<>
Keywords :
distributed memory systems; parallel processing; DRAM; J-Machine architecture; fine-grained distributed memory multicomputer; memory management functions; message-driven processor; processing node; single VLSI chip; Artificial intelligence; Computer architecture; Computer science; Concurrent computing; Laboratories; Memory management; Parallel processing; Parallel programming; Random access memory; Very large scale integration;
Conference_Titel :
Compcon Spring '93, Digest of Papers.
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-8186-3400-6
DOI :
10.1109/CMPCON.1993.289661
