An integrated engineering approach to improve wafer edge yield

Author

Goh, Ivan A N ; Chua, H.S. ; Neo, T.L. ; Soh, Y.Y. ; Chiang, I.C. ; Tan, E.W. ; Tey, G.Y. ; How, K.J. ; Wong, K.F. ; Yeoh, S.W.

Author_Institution

System-on-Silicon Manuf. Co., Singapore, Singapore

fYear

2001

fDate

2001

Firstpage

351

Lastpage

354

Abstract

This paper presents an integrated engineering approach to improve Esort yield at the wafer edge region. In absence of any systematic or parametric issue, the yield loss at the wafer edge region is investigated and initial failure models are then created. Various process improvement schemes which include improved ILD/IMD thickness profile by optimizing Chemical Mechanical Polishing (CMP) recipe, better edge pattern coverage by printing extra lithographic shots and improved Via etch recipes, are explored to resolve the edge losses. These schemes are successfully demonstrated in a production environment with an impressive overall improvement of 5-11 % in Esort yield by reducing the edge loss by more than 70 %. A flow-chart detailing the key improvement steps is presented as well

Keywords

chemical mechanical polishing; etching; failure analysis; integrated circuit yield; Esort yield; ILD/IMD thickness profile; chemical mechanical polishing; edge loss; edge pattern coverage; failure model; flow-chart; integrated engineering; lithographic printing; semiconductor technology; via etching; wafer edge yield; Chemical processes; Etching; Failure analysis; History; Lithography; Planarization; Printing; Production; Pulp manufacturing; Semiconductor device modeling;

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Manufacturing Symposium, 2001 IEEE International

Conference_Location

San Jose, CA

Print_ISBN

0-7803-6731-6

Type

conf

DOI

10.1109/ISSM.2001.962987

Filename

962987