DocumentCode
1840127
Title
The influence of source ballast resistance on current spreading in grounded gate nmosts
Author
De Raad, Gijs
Author_Institution
NXP Semicond., Nijmegen, Netherlands
fYear
2012
fDate
9-14 Sept. 2012
Firstpage
1
Lastpage
10
Abstract
Three-dimensional TCAD simulations of a grounded gate nmost are presented with emphasis on current spreading. The simulations are validated against TLP-results. Back-injection of holes into the source can reduce current spreading, and the amount of back-injection can be controlled by source ballast resistance. Through this mechanism, insufficient source ballast resistance can be limiting to the ESD performance of ggnmosts of a specific layout style as is shown on silicon.
Keywords
MOSFET; technology CAD (electronics); ESD performance; GGNMOST; current spreading; grounded gate NMOST; hole back-injection; silicon; source ballast resistance; specific layout style; three-dimensional TCAD simulation; Charge carrier processes; Current density; Electric potential; Electronic ballasts; Immune system; Logic gates; Slabs;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), 2012 34th
Conference_Location
Tucson, AZ
ISSN
0739-5159
Print_ISBN
978-1-4673-1467-1
Type
conf
Filename
6333282
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